The present invention relates to an apparatus for detecting a pattern alignment error.
Recent, developments in semiconductor device fabrication have led to a technology for fabricating a semiconductor package with a semiconductor device and a circuit board on which the semiconductor package is mounted.
In the development, the semiconductor device, semiconductor package and circuit board may have a multi-layered wiring structure.
For example, a circuit board may include wirings disposed on different layers in order to input or output various types of signals.
In this technology, in order to form the wirings in different layers, a lower wiring is formed on a lower insulation member, and the lower wiring is insulated by an upper insulation member. Subsequently, an upper wiring is formed on the upper insulation member, and the upper wiring is then electrically connected to the lower wiring through a conductive via.
However, when the wirings are disposed on different layers, they are often not aligned accurately, and the upper wiring and lower wiring end up not being connected to each other through the conductive via.
An alignment error of the upper wiring can be easily recognized through a visual test while, but an alignment error of the lower wiring is hard to recognized through a visual test because the lower wiring has been covered by the upper insulation member.